Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!cs.utexas.edu!uunet!van-bc!rsoft!mindlink!a186
From: a186@mindlink.UUCP (Harvey Taylor)
Newsgroups: comp.arch
Subject: Re: parallel systems
Message-ID: <626@mindlink.UUCP>
Date: 24 Oct 89 16:05:24 GMT
Organization: MIND LINK! - British Columbia, Canada
Lines: 33

In Msg-ID: <47279@bbn.COM>, slackey@bbn.com (Stan Lackey) writes:
|In article <20764@usc.edu> vorbrueg@bufo.usc.edu (Jan Vorbrueggen)
| writes:
|>In article <36597@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov
|(Eugene Brooks) writes:
|>
|>> Given equivalent performance interconnect, which rarely occurs
|>> because the message passing machines tend to get short changed on
|>> the comm. hardware, I have found the "shared memory" systems to
|>> have much better communication performance ...
|
|>Eugene, ever seen a transputer? Overhead for receiving or sending a
|>message is 19 cycles (630 ns for a 30 MHz part). The actual transfer
|>is done by a dedicated DMA machine at a maximum rate of 1.7 Mbyte/s
|>unidirectional or 2.4 MByte/s bidirectional.
|
|1) Although it has high? peak bandwidth, the latency is still there.
|The interconnect system waits for the processor to do an access, then
|the processor waits for the interconnect to get the data.  Many
|microseconds go by between the time the CPU needs dependent data and
|it is usable.

  This is getting close to something I have wondered about. How
 applicable is Amdahl's Law to the transputer? How might it be
 affected by the network topology?

  <-Harvey

 "Insanity: A perfectly rational adjustment to an insane world."
                                                -RD Laing
      Harvey Taylor      Meta Media Productions
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