Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!brutus.cs.uiuc.edu!lll-winken!vette!brooks
From: brooks@vette.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: Shared Memory vs. Distributed Systems
Keywords: Shared, distributed, message
Message-ID: <36974@lll-winken.LLNL.GOV>
Date: 27 Oct 89 06:15:11 GMT
References: <20764@usc.edu> <1646@ncrcce.StPaul.NCR.COM> <9605@june.cs.washington.edu> <6708@pt.cs.cmu.edu>
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Organization: Lawrence Livermore National Laboratory
Lines: 16

In article <6708@pt.cs.cmu.edu> sc@klingon.pc.cs.cmu.edu (Siddhartha Chatterjee) writes:
>Well, yes and no.  On a bus-connected machine like the Encore you have
>snoopy caches that keep the data consistent and KEEP IT CLOSE TO THE
>PROCESSOR.  On something like a Butterfly, the default behaviour is that
>shared data is not cached; so yes, memory is consistent, but you have to go
>out across the network to access it.  You can do explicit cache flushing in
>software, but that's a different game.
One can have hardware enforcement of coherence of caches in a scalable system.
Many proposed mechanisms exist in the literature for this.  I think that
these system are much too complex to "guess" as to the best method, but
simulation results will tell the story and vendors will be able to make
suitable hardware available in the next couple of years.  Coherent cache
systems are just too friendly to not to build them.


brooks@maddog.llnl.gov, brooks@maddog.uucp