Path: utzoo!attcan!utgpu!utstat!jarvis.csri.toronto.edu!mailrus!purdue!bu-cs!encore!encore.UUCP
From: jdarcy@encore.UUCP (Jeff d'Arcy)
Newsgroups: comp.arch
Subject: Re: specmarks
Message-ID: <10248@encore.Encore.COM>
Date: 27 Oct 89 15:32:45 GMT
References: <2430@convex.UUCP>
Sender: news@Encore.COM
Lines: 12

swarren@eugene.uucp (Steve Warren):
> Did you really use clock frequency?  Or did you use bus cycles, which makes
> much more sense?  For example, 680x0 arch. uses four clock cycles per
> memory access.  So you need to divide the clock freq. by four to get
> comparable numbers.  Etc.

This is a particularly important point when comparing RISC vs. CISC.  One of
the major goals of CISC is to allow higher clock frequencies by simplifying
the design, but memory access time is another matter.

Jeff d'Arcy     OS/Network Software Engineer     jdarcy@encore.com
  Encore has provided the medium, but the message remains my own