Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!eecg.toronto.edu!vuillamy
From: vuillamy@eecg.toronto.edu (Jean-Michel Vuillamy)
Newsgroups: comp.lsi.cad
Subject: Automatic transistors sizing
Keywords: CAD,VLSI,CMOS
Message-ID: <1989Oct26.115326.19494@jarvis.csri.toronto.edu>
Date: 26 Oct 89 15:53:26 GMT
Organization: EECG, University of Toronto
Lines: 10

In the paper "High-Speed CMOS Circuit technique" (IEEE Journal of Solid-State
Circuits, Vol 24 n. 1, February 1989), the authors J.Yuan and C. Svensson are
describing some tools for automatic optimization through device sizing. Two 
programs are mentioned : SLOP and TMODS.

Could you mail me some information about those tools (or any others : I would
be interested in public domain software). If I'll get enough answers, I will
publish them later.

			Jean-Michel Vuillamy