Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!tank!eecae!netnews.upenn.edu!dsl.cis.upenn.edu!david
From: david@dsl.cis.upenn.edu (David P. Feldman)
Newsgroups: comp.sys.ibm.pc
Subject: IBM AT Bus Timing
Keywords: DMA, 16 bit cycles
Message-ID: <16089@netnews.upenn.edu>
Date: 28 Oct 89 23:39:42 GMT
Sender: news@netnews.upenn.edu
Reply-To: david@dsl.cis.upenn.edu (David P. Feldman)
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Organization: University of Pennsylvania
Lines: 19

Folks,

I am a new subscriber to this group, so please excuse my ignorance on this
subject if this has been gone over before.

I am in need of data concerning the timing of DMA and 16 bit bus transfers on
the IBM AT bus.  With regards to the DMA transfers, I need to know the timing
restrictions on the DREQ signals.  For 16 bit cycles, I need to know the same
for the -I/O CS 16 signal.  These signals are sent to the CPU from I/O boards.

I am especially looking for pointers to reference materials, but any data you
could mail (hard or electronic) me would be appreciated.  I will re-imburse
for any help.

_   /|					Dave Feldman
\'o.O'					david@dsl.cis.upenn.edu
=(___)=		Ok, cough!
   U					DSL - land of wonder and enchantment
ACK! PHHT!