Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.sys.m68k
Subject: Re: 68000 timing skew of !AS vs !xDS
Message-ID: <23250@cup.portal.com>
Date: 21 Oct 89 17:38:31 GMT
References: <552@crash.cts.com>
Organization: The Portal System (TM)
Lines: 9

They don't spec skew between AS and DS.  Althought they are shown to be
the same on the timing diagram, for true worst-case design you have to
assume that the delay from clock to AS is at the minimum, and clock to DS
is at the maximum (or vice versa).  Obviously, this is overly conservative,
but I see no way to pick a "reasonable" but safe value.

Anyone from Moto willing to comment?

Michael Slater, Microprocessor Report   mslater@cup.portal.com