Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!brutus.cs.uiuc.edu!ginosko!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.unix.i386
Subject: Re: Cache performance on 386 boards running Unix
Message-ID: <1480@crdos1.crd.ge.COM>
Date: 25 Oct 89 20:00:34 GMT
References: <919@umigw.MIAMI.EDU> <416@ssp2.idca.tds.philips.nl>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: GE Corp R&D Center
Lines: 19

In article <416@ssp2.idca.tds.philips.nl>, pb@idca.tds.PHILIPS.nl (Peter Brouwer) writes:
|  This depends on the size/working set of your applications you use.
|  Most caches are 64k = 16 pages. So if you have large applications with
|  a working set ( number of pages it used during execution ) the cache is'nt
|  a great help. 

  Micro caches don't work in 4k pages, so what has this to do with
anything? I suspect you're thinking of mainframe cache which may work
in larger chunks. 4, 16, and 32 byte cache chunks are mentioned by
manufacturers, I think someone used 64 bytes, but I haven't got the
name.

  If anyone has an Intel cache controller spec sheet handy, please
contribute. 
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon