Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!eos!shelby!portia!dhinds
From: dhinds@portia.Stanford.EDU (David Hinds)
Newsgroups: comp.unix.i386
Subject: Re: Cache performance on 386 boards running Unix
Summary: Intel Cache Controller
Message-ID: <6109@portia.Stanford.EDU>
Date: 25 Oct 89 20:56:19 GMT
References: <919@umigw.MIAMI.EDU> <416@ssp2.idca.tds.philips.nl> <1480@crdos1.crd.ge.COM>
Sender: David Hinds <dhinds@Portia.stanford.edu>
Organization: Stanford University
Lines: 21

In article <1480@crdos1.crd.ge.COM>, davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) writes:
>   If anyone has an Intel cache controller spec sheet handy, please
> contribute. 

I don't have the spec's, but as I understand it, the Intel chip is a
"2-way set-associative" cache controller.  Each entry in the cache
has two parts: a physical-memory address to which it corresponds, and
a copy of the data at that address (32 bits, I think).  To speed up
the check to see if something is in the cache, there are only two
entries in the cache where any given physical address might reside.
A 'set' of physical addresses are 'associated' with each pair of
cache entries.  When the 80386 sends out a physical address, the
cache controller figures out which two entries might contain the data
(probably using the top bits of the address as an index into the cache),
checks those two entries to see if either address matches the request,
and either returns the data from the cache or polls main memory.
A 64K cache is built from 8 8K-by-8bit static RAM chips, to be 64 bits
wide, so that each cache entry has room for a 32-bit address and 32 bits
of data.  So it actually has 32K of data.
                               -David Hinds
                                dhinds@portia.stanford.edu