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From: ylkingsbury@watdragon.waterloo.edu (Yvonne Kingsbury)
Newsgroups: ont.events,uw.talks,uw.cs.grad
Subject: ICR Colloquium
Keywords: Digital
Message-ID: <17594@watdragon.waterloo.edu>
Date: 27 Oct 89 14:30:46 GMT
Distribution: ont
Organization: U of Waterloo, Ontario
Lines: 28

ICR Colloquium

HIgh Level Synthesis of Digital Hardware

Dr. Raul Camposano
IBM Thomas J. Watson Research Centre

Date: Wednesday, November 1, 1989
Time: 3:30 p.m.
Place: Davis Centre, Room 1302

Abstract

High level synthesis is the automatic design of a register-transfer
level structure that realizes a formally specified behaviour.  This lecture
gives an overview of the different issues involved in high-level synthesis
, i.e., design representation, high-level optimizations, scheduling,
allocation and interface to other design tools, mainly logic synthesis.
It emphasizes the two central problems in high-level synthesis: scheduling
and allocation.  In synchronous designs, scheduling consists of assigning
operations to discrete time slots called control steps.  The hardware for the
execution of the operations is defined during allocation.  Scheduling
and allocation are interrelated and depend on each other.  The main
algorithms for these transformations developed in Yorktown are shown.  Finally
some open problems such as design verification, design with constraints and
pipeline synthesis are addressed.

Coffee and cookies will be served.  Everyone welcome.