Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!brutus.cs.uiuc.edu!rpi!batcomputer!cornell!uw-beaver!Teknowledge.COM!unix!hplabs!hp-sdd!ucsdhub!sdcsvax!beowulf!kim
From: kim@beowulf.ucsd.edu (Geoffrey K Kim)
Newsgroups: comp.sys.amiga
Subject: Re: Speed
Message-ID: <7395@sdcsvax.UCSD.Edu>
Date: 8 Nov 89 07:10:41 GMT
References: <649@milton.acs.washington.edu>
Sender: nobody@sdcsvax.UCSD.Edu
Reply-To: kim@beowulf.UCSD.EDU (Geoffrey K Kim)
Organization: EE/CS Dept. U.C. San Diego
Lines: 15

In article <649@milton.acs.washington.edu> axjjb@acad3.fai.alaska.edu writes:
>I am hopelessly confused about the 25 mhz accelerator board.  What do they mean
>by 32 bit ram?  Is it accessing Ram at 32 bit increments?  I am also wondering
>what is the exact bit access of the cpu..(ie..16 or 32)

I kinda had a related query regarding the '020 and '030 CPU cards:  Isn't
the Amiga's bus still only 16 bits wide?  Since all video data has to be
sent over this, doesn't this present a bottleneck?  (I'd really like an
A2000 with the next '030 board from CBM, but this question has kinda been 
lurking in the background.)

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| kim @beowulf.UCSD.EDU (Home of the Garden Weasles)                  |
|        "... ENGAGE!" -- Jean Luc Picard, STTNG                      |
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