Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!rpi!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Can I Trust Performance Results?
Message-ID: <1543@crdos1.crd.ge.COM>
Date: 3 Nov 89 16:11:16 GMT
References: <89110221162151@masnet.uucp>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: GE Corp R&D Center
Lines: 23

In article <89110221162151@masnet.uucp>, wayne.ho@f526.n250.z1.fidonet.org (wayne ho) writes:
|                                    Because I have RAM which is fast 
|  enough to run 0 wait states, non-interleaved (I suppose true 0 wait 
|  state.. not .7 wait states) it will be faster than interleaving the 
|  RAM.  This is my educated guess.

  Remember that access time and cycle time are involved here. Access
time is the time to get data from a memory. Cycle time is the time to
get the *next* access. Most DRAM has a cycle time longer than the access
time, while for static RAM they are the same. Not all memory rated at
60ns can be accessed EVERY 60ns. This doesn't mean that your chips won't
do what you expect, but that you and other users should realize that
interleave is designed to avoid just this problem.

  When I last had a look at real data (measured by a competent user),
100ns chips typically could only go 140-160ns cycles time. If someone
has more recent data I would like to see it, mine is back from the days
when 100ns was hot stuff.
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon