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From: noah@Apple.COM (Noah Price)
Newsgroups: comp.sys.mac.hardware
Subject: Re: Mac IIci Wait states (was Re: Mac IIci benchmarks)
Summary: Both caches are enabled and bursting.
Message-ID: <36281@apple.Apple.COM>
Date: 7 Nov 89 04:07:59 GMT
References: <6283@tekgvs.LABS.TEK.COM> <36198@apple.Apple.COM> <6303@tekgvs.LABS.TEK.COM>
Organization: Apple Computer Inc, Cupertino, CA
Lines: 14

In article <6303@tekgvs.LABS.TEK.COM> larryh@tekgvs.LABS.TEK.COM (Larry Hutchinson) writes:
>The '030 user's manual says "The data burst enable bit must be set to
>enable burst filling of the data cache."
>
>Anyone know if this bit is set when running user code?

Yes, both the data and instruction caches are enabled and burst enabled
during the boot process.

noah

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noah@apple.com                                    Mac IIci Hardware Design Team
..!{sun,decwrl}!apple!noah                                 Apple Computer, Inc.