Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.mac.hardware
Subject: Re: Mac IIci Wait states (was Re: Mac IIci benchmarks)
Message-ID: <8426@cbmvax.UUCP>
Date: 7 Nov 89 17:48:05 GMT
References: <6303@tekgvs.LABS.TEK.COM>
Organization: Commodore Technology, West Chester, PA
Lines: 23

in article <6303@tekgvs.LABS.TEK.COM>, larryh@tekgvs.LABS.TEK.COM (Larry Hutchinson) says:

> why does the iici use synchronous access?  to improve the cache performance perhaps?  

synchronous cycle mode is required for burst cache fills.  most '030
systems that support burst fills always use synchronous mode, simply
because, once you fulfill the requirements for burst mode, you work with
synchronous mode regardless of whether you're actually bursting or not. 

there are two other reasons for using synchronous mode (other than for
burst support).  the most obvious is that synchronous cycles are a minimum
of two clocks, versus three for asynchronous cycles.  the other reason is
that synchronous cycles are terminated 1/2 clock later, so if you're
waiting for a termination from something, there may be less lag with the
synchronous mode (though the synchronous cycle termination must obey
proper setup and hold times to the 68030, while the asynchronous signals
can come in at any time).

> Larry Hutchinson, Tektronix, Inc. PO Box 500, MS 50-383, Beaverton, OR 97077
-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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