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From: foperator@tekno.chalmers.se (Daniel Berglund)
Newsgroups: sci.electronics
Subject: "CAS before RAS"-refresh
Message-ID: <3056@tekno.chalmers.se>
Date: 1 Nov 89 22:14:30 GMT
Organization: Chalmers Univ. of Technology, Gothenburg, Sweden
Lines: 13

I have a question about the "CAS-before-RAS" refresh mode found in certain
DRAMs (specifically, 4464 (64Kx4)). The data sheet states that the chip will
generate the row address internally. Does this mean that the only thing I will
have to do to keep the memory refreshed is to toggle CAS and RAS with the
prescribed timing every once in a while? As I just have spent some hours to
design a clever (?) network of counters, gates, buffers etc in order to keep
track of the very same row address, this seems a little bit too good to be
true. Please tell me that it is. :-)

Thanks in advance,
-- 
Daniel Berglund       (foperator@tekno.chalmers.se, BITNET: FOP@SECTHF51)
Chalmers University of Technology, G|teborg, Sweden