Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!cs.utexas.edu!uunet!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: sci.electronics
Subject: Re: "CAS before RAS"-refresh
Message-ID: <8390@cbmvax.UUCP>
Date: 2 Nov 89 16:27:46 GMT
References: <3056@tekno.chalmers.se>
Organization: Commodore Technology, West Chester, PA
Lines: 22

in article <3056@tekno.chalmers.se>, foperator@tekno.chalmers.se (Daniel Berglund) says:

> I have a question about the "CAS-before-RAS" refresh mode found in certain
> DRAMs (specifically, 4464 (64Kx4)). The data sheet states that the chip will
> generate the row address internally. Does this mean that the only thing I will
> have to do to keep the memory refreshed is to toggle CAS and RAS with the
> prescribed timing every once in a while? 

Yup, as long as you get enough CAS-before-RAS cycles out within the prescribed 
refresh time, you're refreshing.  Each DRAM has an internal counter than gets
banged on each CAS-before-RAS refresh cycle.  MUCH easier than building a row
counter and all, if you're building the memory controller by hand (eg, TTL/PAL).
This feature started showing up around the time 256K desity DRAMs came out
(256kx1 and 64kx4), so it's in most of those, and far as I know all 1 meg and
higher density parts.

> Daniel Berglund       (foperator@tekno.chalmers.se, BITNET: FOP@SECTHF51)
> Chalmers University of Technology, G|teborg, Sweden
-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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                    Too much of everything is just enough