Xref: utzoo sci.space:15151 sci.space.shuttle:3957 sci.astro:5607 Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!nisca.ircc.ohio-state.edu!gem.mps.ohio-state.edu!brutus.cs.uiuc.edu!apple!usc!henry.jpl.nasa.gov!elroy.jpl.nasa.gov!news From: stevo@uniblab.Jpl.Nasa.Gov (Steve Groom) Newsgroups: sci.space,sci.space.shuttle,sci.astro Subject: Re: Computer Message-ID: <1989Oct31.173058.15920@elroy.jpl.nasa.gov> Date: 31 Oct 89 17:30:58 GMT References: <1368@orbit.UUCP> Reply-To: stevo@elroy.Jpl.Nasa.Gov (Steve Groom) Organization: Image Analysis Systems Grp, JPL Lines: 17 In article <1368@orbit.UUCP> schaper@pnet51.orb.mn.org (S Schaper) writes: [ referring to the future use of "modern" processors for flight hardware, in particular a version of the 8086 ] >I'd opt for 80860's that are rad-hardened, or 88k's in parallel... Of course you would. Believe me, the people responsible for flight software would too. The problem is that it's not a trivial task to design and produce rad-hard parts. You don't just whip up a special version of a chip in a few months and stick it in a spacecraft. That's why a rad-hard version of the 8086 is just now being discussed for use, because has taken this long to produce it. Personally, I'd rather see them using a SPARC :-) -- Steve Groom, Jet Propulsion Laboratory, Pasadena, CA stevo@elroy.jpl.nasa.gov {ames,usc}!elroy!stevo