Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!samsung!usc!apple!sun-barr!newstop!sun!amdcad!neutron!tim From: tim@neutron.amd.com (Tim Olson) Newsgroups: comp.arch Subject: Re: AMD 29000 - no (data) cache? Message-ID: <27967@amdcad.AMD.COM> Date: 9 Nov 89 14:39:10 GMT References: Sender: news@amdcad.AMD.COM Reply-To: tim@amd.com (Tim Olson) Organization: Advanced Micro Devices, Inc., Austin, Texas Lines: 15 Summary: Expires: Sender: Followup-To: In article aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) writes: | Are there any variants of the AMD 29000 that have on-chip data caches? | (Not BTC or TLB or I-cache) | | My last spec sheet is 1987, which is a bit dated. Sorry about being late in responding here -- our main mail/news server has been down for 1 1/2 weeks. Anyway, there are currently no members of the 29K processor family that have on-chip data caches, at least in the traditional sense. You can consider the large register file to be a compiler-controlled scalar stack cache. -- Tim Olson Advanced Micro Devices (tim@amd.com)