Xref: utzoo comp.arch:12327 comp.compilers:691 Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!lotus!esegue!compilers-sender From: cassel@sce.carleton.ca Newsgroups: comp.arch,comp.compilers Subject: Re: Compiler optimization and RISC. Keywords: List of references. Message-ID: <1989Nov9.153132.1437@esegue.segue.boston.ma.us> Date: 9 Nov 89 15:31:32 GMT References: <1989Nov3.153807.1427@esegue.segue.boston.ma.us> <1989Nov8.012429.391@esegue.segue.boston.ma.us> Sender: compilers-sender@esegue.segue.boston.ma.us Reply-To: cassel@sce.carleton.ca Organization: Systems Eng., Carleton Univ., Ottawa, Canada Lines: 18 Approved: compilers@esegue.segue.boston.ma.us Here are a few pointers for code optimization on RISC. 1. Coding Guidelines for Pipelined Processors, James W. Rymarcyk, International Business Machines, ACM 0-89791-066-4 2. Hennessy, J.L. and Gross, T.R., "Postpass Code Optimization of Pipeline Constraints", ACM TOPLAS, Vol. 5, No 3., July, 1983. 3. T.R. Gross, Code Optimization of Pipeline Constraints", PHD Dissertation, Standford University, Auguat 1983. -- Ron Casselman (613) 788-5726 Systems and Computer Engineering, uunet!mitel!sce!cassel (uucp) Carleton University, cassel@sce.carleton.ca (bitnet) Ottawa, Ontario, Canada K1S 5B6. -- Send compilers articles to compilers@esegue.segue.boston.ma.us {spdcc | ima | lotus}!esegue. Meta-mail to compilers-request@esegue. Please send responses to the author of the message, not the poster.