Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!zds-ux!gerry
From: gerry@zds-ux.UUCP (Gerry Gleason)
Newsgroups: comp.arch
Subject: Re: RISC vs CISC (rational discussion, not religious wars)
Message-ID: <6@zds-ux.UUCP>
Date: 9 Nov 89 19:09:33 GMT
References: <503@ctycal.UUCP> <1579@crdos1.crd.ge.COM> <31027@obiwan.mips.COM>
Reply-To: gerry@zds-ux.UUCP (Gerry Gleason)
Organization: Zenith Data Systems
Lines: 19

In article <31027@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>In article <1579@crdos1.crd.ge.COM> davidsen@crdos1.UUCP (bill davidsen) writes:
>>  I don't think any major chips are being designed in 6 months, or 18.
>>At least not CPUs. I believe Intel said that the 486 design cycle was
>>started about five years ago. Feel free to correct this if you have a
>>better source than _Info World_.

>Fujitsu SPARC . . .
>Or how about the Cypress full-custom SPARC?  Both of these were designed
>and taped-out in well under 18 months.
> . . . R2000 . . .  in 9 months.

I assume you are only stating the design cycles for these RISC processors,
and not disputing his guess about the 486.  Even if it is more like three
years, that's still a big win in design cycle time for RISCs, and what about
man years invested in these processors.  These wins in design cycle are
probably more significant than the performance issue (not insignificant itself).

Gerry Gleason