Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!fernwood!decwrl!kaputt.dec.com!neideck
From: neideck@kaputt.dec.com (Burkhard Neidecker-Lutz)
Newsgroups: comp.arch
Subject: On chip caches (was RISC vs. CISC)
Message-ID: <8911100815.AA00800@decwrl.dec.com>
Date: 10 Nov 89 08:15:13 GMT
Organization: Digital Equipment Corporation
Lines: 27

For those that believe they can get by without at least some on-chip
cache (never mind RISC or CISC, as long as things move fast I'll take it),
there is an interesting paper:

	Integration and Packaging Plateaus of Processor Performance
	Norman P. Jouppi
	International Conference of Computer Design
	IEEE, Cambridge, Massachussets, October 2-4 1989

He starts out with some of the exotic ideas used by the high performance
folks (Cray, Prisma) and their packaging (well, the VAX9000 falls somewhat
in the same category) and then dismisses all that for a very simple reason:

He doesn't count gate delays (go ahead, choose a 0ns technology) but only
counts the times it takes to get off-chip, off-board, etc. Interesting
thought experiment and even better when you have a simulator to "design"
a processor and run programs on it like Norman has. It runs variations of
the MultiTitan research processor, a very MIPS-like RISC machine.

Makes for little guessing and relatively accurate numbers. It turns out that
there is a gap of a factor of about 10 to 20 between machines that have
to go for an external cache each cycle and those that do not have to. The
limiting factor is the interconnect delay and that cannot be arbitrarily 
lowered. The whole data is impossible to reproduce here, read the paper.

		Burkhard Neidecker-Lutz, Digital CEC Karlsruhe,
					 Project NESTOR