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From: rogerk@mips.COM (Roger B.A. Klorese)
Newsgroups: comp.arch
Subject: Re: MIPS Co's 55 MIPS machine
Message-ID: <31176@servitude.mips.COM>
Date: 10 Nov 89 20:04:12 GMT
References: <19147@pasteur.Berkeley.EDU> <280003@hpdml93.HP.COM> <12@zds-ux.UUCP>
Reply-To: rogerk@mips.COM (Roger B.A. Klorese)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 22

In article <12@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
>In article <280003@hpdml93.HP.COM> sritacco@hpdml93.HP.COM (Steve Ritacco) writes:
>>It is an ECL implementation fabb'ed by BIT, as I understand it.
>>More info would be appreciated, especially any architectural
>>enhancements or changes over the R3000.
>Are you both talking about the same chip?  The BIT processor that I
>know about is a SPARC processor.  There was an article in High Performance
>Systems about it.  I believe they quoted an 80MHz clock rate and 60 MIPS
>performance, and also claimed that at least some of the early chips would
>run at 100MHz.

No, BIT has also fabbed for MIPS the R6000 chipset.  [You're confused about
this one because we didn't preannounce it by quite so long.  ;-)  Plus, it's
not announced as a BIT product, but as a MIPS system component.]  We are 
getting 55 MIPS (on our benchmark suite which shows the SPARCstation 3xx
series as 16 MIPS, for comparison) at 67MHz; this may improve some by FCS
early in 1990.
-- 
ROGER B.A. KLORESE      MIPS Computer Systems, Inc.      phone: +1 408 720-2939
928 E. Arques Ave.  Sunnyvale, CA  94086                        rogerk@mips.COM
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"I want to live where it's always Saturday."  -- Guadalcanal Diary