Path: utzoo!bnr-vpa!bnr-fos!bigsur!bnr-rsc!bcarh61!schow From: schow@bcarh61.bnr.ca (Stanley T.H. Chow) Newsgroups: comp.arch Subject: Re: RISC vs CISC (rational discussion, not religious wars) Summary: RISC != simple Message-ID: <1352@bnr-rsc.UUCP> Date: 10 Nov 89 19:15:19 GMT References: <503@ctycal.UUCP> <31031@winchester.mips.COM> Sender: news@bnr-rsc.UUCP Reply-To: schow%BNR.CA.bitnet@relay.cs.net (Stanley T.H. Chow) Organization: BNR Ottawa, Canada Lines: 65 Followup-To: Keywords: In article <31031@winchester.mips.COM> mash@mips.COM (John Mashey) writes: > >The die area issue has been widely misinterpreted. Let me summarize some >of the various arguments for RISC vs CISC and die size: > [...] >ARGUMENT 4: But when you can get zillions** of transistors on a die, it > it doesn't matter. > COMMENT 1: We haven't gotten enough transistors to make anybody > happy yet ("happy" means VLSI designers wandering around > saying "I have so much space I don't know what to do with it") > and we're not likely to get enough any time real soon. > COMMENT 2: Of course, this all remains to be seen, but: > COMMENT 3: More transistors will help everything, however, it may be > that the "limiting factor" will be not die space, > but COMPLEXITY in critical paths and exception-handling. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Please note that "complexity" is essentially independent of the RSIC/CSIC debate. I defy anyone to call the M88k as simple :-) It is certainly true that i86 (or any other micro) has had its share of problems. However, I would score the problems to the "Venerable Architecture" instead. It is by no means clear that CISC architecture must always be nasty in this respect. The "Zillion transistor" question is essentially another design trade-off: is it better to use the transistors for bigger cache? more pipeline stages? fatter pipelines? more execution units? .... Of course, once the architecture is chosen, many of the trade-offs become obviouse. IMHO, CSIC leaves many of the choices open, allowing more paths to be determined later. [Structured Software people think delaying choices is a good stratagy. You may or may not agree. :-)]. > >Do weird and occasional effects matter? Maybe, maybe not. Observe that >a 6-month difference is a long time these days, and if it takes 6 months >more to get a design really right enough that reputable companies will >ship it, that's a noticable difference. > Certainly 6 months make a difference. It is also true that even 2 years make little difference. It all depends on the market and the perspective. How many RISC chips beat the 486 to market? What difference did it make? These days, software is KING. In the commercial market place, Compatibility is also very important. Even in the new designs that don't care about old software, I would think designers (at least the design managers) should look at the long term evolution of the architecture before settling on a particular CPU chip. The only occasions when 6 months *really* matter is a race to open up a new area. It's been a long time since those kinds of excitment in the CPU & memory market. Examples are the *first* one-chip CPU (the 4004/8008), the first DRAM, the first EEPROM, etc. When I can also buy the same functionality, 6 months is only cost-optimization. Stanley Chow BitNet: schow@BNR.CA BNR UUCP: ..!psuvax1!BNR.CA.bitnet!schow (613) 763-2831 ..!utgpu!bnr-vpa!bnr-rsc!schow%bcarh61 Me? Represent other people? Don't make them laugh so hard.