Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!apple!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: RISC vs CISC (rational discussion, not religious wars)
Keywords: Die Space
Message-ID: <31198@winchester.mips.COM>
Date: 11 Nov 89 02:37:44 GMT
References: <503@ctycal.UUCP> <15126@haddock.ima.isc.com> <28942@shemp.CS.UCLA.EDU> <31097@winchester.mips.COM> <28985@shemp.CS.UCLA.EDU> <9769@june.cs.washington.edu>
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Inc.
Lines: 39

In article <9769@june.cs.washington.edu> kolding@june.cs.washington.edu.cs.washington.edu (Eric Koldinger) writes:

>    Why not provide both on-chip and off-chip cache ($).  In the chip of the
>    future, a 50-100Mhz part, keeping the processor fed from an off chip cache
>    will be quite a bear.  The off-chip communication speeds are probably going
>    to be substantially slower than what you can achieve on-chip, so feeding an
>    instruction per cycle into the chip might improve almost impossible,
....
Some relevant recent papers include:

Wen-Hann Wang, Jean-Loup Baer, Henry M. Levy, "Organization and Performance
of a Two-Level Virtual-Real Cache Hierarchy", 16th Ann. Int. Symposium
on Computer Architecture, May-June 1989, Jerusalem, Israel.
ACM SIGARCH 17, 3 (June 1989), 140-148.  [Univ. of Washington people,
using virtual first-level and real second-level caches: get fast cycle
from first level, high hit-rate from second.  Grossly similar scheme to
MIPS MC6280, for same reasons.

Steven Pryzbylski, Mark Horowitz, John Hennessy, "Characteristics of
Performance-Optimal Multi-Level Cache Hierarachies", (same as above), 114-121.
A good quote from the abstract:
	"The increasing speed of new generation processors will exacerbate
the already large difference between CPU cycle times and main memory
access times.  As this difference grows, itwill be increasingly difficult
to build single-level caches that are both fast enough to match these fast
cycle times and large enough to effectively hide the main memory
access times....  This change in relative importance of cycle time
and miss rate makes associativity more attractive and increases the
optimal cache size for second-level caches over what they would be
for an equivalent single-level cache system."

Note, of course, that many 68020 systems used external caches along
with the internal ones, and various sperminis and mainframes have
used such things for some time.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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