Path: utzoo!censor!geac!jtsv16!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: RISC vs CISC (rational discussion, not religious wars)
Message-ID: <1591@crdos1.crd.ge.COM>
Date: 9 Nov 89 21:19:25 GMT
References: <503@ctycal.UUCP> <1579@crdos1.crd.ge.COM> <31027@obiwan.mips.COM>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: GE Corp R&D Center
Lines: 21

In article <31027@obiwan.mips.COM>, mark@mips.COM (Mark G. Johnson) writes:

|  Just to name a couple from our esteemed colleagues in the SPARC camp,
|  how about the original Fujitsu SPARC (the one in the 4/260)?  Its
|  design schedule & history was published in _High_Performance_Systems.
|  Or how about the Cypress full-custom SPARC?  Both of these were designed
|  and taped-out in well under 18 months.

  I think we're talking different things as design time here, I was
talking about the time from "let's build a CPU" to a working part.
Taking a part with known word size, register layout and instruction set
is a subset of that. A SPARC port looks to me like "how do we do it"
with out the "what do we do" phase.

  Since you mentioned the R2000, can you determine the elapsed time for
the whole process?
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon