Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!wuarchive!wugate!uunet!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: MIPS Co's 55 MIPS machine
Message-ID: <23945@cup.portal.com>
Date: 12 Nov 89 04:08:56 GMT
References: <19147@pasteur.Berkeley.EDU> <280003@hpdml93.HP.COM>
Organization: The Portal System (TM)
Lines: 29

>> Anybody have information about the new 55 MIPS machine that MIPS Co.
>> announced?  For example, what technology is the processor, ECL?  What are th
e
>> specs for the cache design?  What is the memory and I/O bandwidth?
>> 
>> 	Chris Perleberg
>
>It is an ECL implementation fabb'ed by BIT, as I understand it.
>More info would be appreciated, especially any architectural
>enhancements or changes over the R3000.

The new machine uses the R6000 CPU, which is currently being made by BIT.
BIT is also making the R6010, a floating-point controller, and the R6020,
a system bus interface chip.  The FPC includes the adder/subtracter and 
registers, but the mul/div is in a standard BIT chip, which also has square
root.  The MIPS cpu implementation also uses a bunch of ECL gate arrays
from Sony.

MIPS is making the BIT and Sony chips available on a limited basis.  Sometime
next year, they will become available from NEC and Sony.

MIPS is not releasing full details of the architectural extensions yet. 
There are new instructions to support some new capabilities of the FP
hardware, some multiprocessor instructions, and some support for dynamically
changing "endian-ness".

Michael Slater, Microprocessor Report   mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto, CA 94306  415/494-2677
sample issue sent on request