Path: utzoo!censor!geac!jtsv16!uunet!zds-ux!gerry
From: gerry@zds-ux.UUCP (Gerry Gleason)
Newsgroups: comp.arch
Subject: Re: MIPS Co's 55 MIPS machine
Message-ID: <12@zds-ux.UUCP>
Date: 10 Nov 89 16:22:16 GMT
References: <19147@pasteur.Berkeley.EDU> <280003@hpdml93.HP.COM>
Reply-To: gerry@zds-ux.UUCP (Gerry Gleason)
Organization: Zenith Data Systems
Lines: 16

In article <280003@hpdml93.HP.COM> sritacco@hpdml93.HP.COM (Steve Ritacco) writes:
>> Anybody have information about the new 55 MIPS machine that MIPS Co.
>> announced?  For example, what technology is the processor, ECL?  What are the
>> specs for the cache design?  What is the memory and I/O bandwidth?

>It is an ECL implementation fabb'ed by BIT, as I understand it.
>More info would be appreciated, especially any architectural
>enhancements or changes over the R3000.

Are you both talking about the same chip?  The BIT processor that I
know about is a SPARC processor.  There was an article in High Performance
Systems about it.  I believe they quoted an 80MHz clock rate and 60 MIPS
performance, and also claimed that at least some of the early chips would
run at 100MHz.

Gerry Gleason