Path: utzoo!bnr-vpa!bnr-fos!bigsur!bnr-rsc!bcarh61!schow
From: schow@bcarh61.bnr.ca (Stanley T.H. Chow)
Newsgroups: comp.arch
Subject: 55 MIPS & 66 MIPS
Message-ID: <1358@bnr-rsc.UUCP>
Date: 13 Nov 89 05:43:12 GMT
Sender: news@bnr-rsc.UUCP
Reply-To: schow%BNR.CA.bitnet@relay.cs.net (Stanley T.H. Chow)
Organization: BNR Ottawa, Canada
Lines: 31
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It seems to me the MIPS 55 MIPS (@ 60 MHz?) ECL system (chip set?)
is the "classical" approach for RISC designs to get higher through-
put. They do it by upping the clock-rate.

Intel has gone the SuperScalar route. Their i960CA is said to be
66 MIPS @ 33 MHz. They have put the cleverness into multiple
execution units.

Here is the $64,000 question:

   Which part is easier to integrate into a real system? 

Please note that we have concrete real examples here. Theoratical
discussion is nice, but real data-points are more interesting.

Other interesting question:

   Which system has a larger "domain" over which it actually
   achives quoted figures?

   What other systems/chips/... are claiming over 50 MIPS?

   How do these systems compare in terms of cost (design and per unit)?



Stanley Chow        BitNet:  schow@BNR.CA
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(613) 763-2831		     ..!utgpu!bnr-vpa!bnr-rsc!schow%bcarh61
Me? Represent other people? Don't make them laugh so hard.