Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!pt.cs.cmu.edu!andrew.cmu.edu!bader+
From: bader+@andrew.cmu.edu (Miles Bader)
Newsgroups: comp.arch
Subject: Re: RISC multiprocessors
Message-ID: <sZLhtay00UkaIj6al2@andrew.cmu.edu>
Date: 13 Nov 89 15:31:50 GMT
References: <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM>,
	<23963@cup.portal.com>
Organization: Information Technology Center, Carnegie Mellon, Pittsburgh, PA
Lines: 7
In-Reply-To: <23963@cup.portal.com>

mslater@cup.portal.com (Michael Z Slater) writes:
> Plus, the R3000 cache is write-through, and a reasonable
> multiprocessor system needs write-back caches.

Why?

-Miles