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From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: ERISC???
Message-ID: <48135@bbn.COM>
Date: 13 Nov 89 17:21:22 GMT
References: <1989Oct19.155752.13028@mentor.com> <126596@sun.Eng.Sun.COM>
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Reply-To: slackey@BBN.COM (Stan Lackey)
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Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <126596@sun.Eng.Sun.COM> khb@sun.UUCP (Keith Bierman - SPD Advanced Languages) writes:
>In article <1989Oct19.155752.13028@mentor.com> geraldp@mentor.com (Gerald Page) writes:
>>2.  All instructions (operations) consume a single processor cycle with the
>>    possible exceptions of LOAD and STORE.
>I know of NO machine which performs singe floating point OPS in 1
>cycle (some machines can achieve 1 fop/cycle when the pipes can be
>kept full). Are there counterexamples, or is #2 simply at variance
>with reality ?

The Alliant does fp in one cycle. In fact anything that uses BIT FP chips
that cycles even up to speeds of 20MHz or more can do it, provided the
operand passing is pipelined properly.
-Stan