Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!convex!eugene!swarren
From: swarren@eugene.uucp (Steve Warren)
Newsgroups: comp.arch
Subject: Re: RISC multiprocessors
Message-ID: <3028@convex.UUCP>
Date: 13 Nov 89 13:47:38 GMT
References: <30969@winchester.mips.COM> <183@cvbnet.Prime.COM>
Sender: news@convex.UUCP
Reply-To: swarren@convex.COM (Steve Warren)
Organization: Convex Computer Corporation, Richardson, Tx.
Lines: 26

In article <183@cvbnet.Prime.COM> aperez@cvbnet.UUCP (Arturo Perez x6739) writes:
>From article <30969@winchester.mips.COM>, by mash@mips.COM (John Mashey):
>> In article <516@baird.cs.strath.ac.uk> jim@cs.strath.ac.uk writes:
>> .......
>> This is all true, but just to make sure there is no ambiguity,
>> and to head off a potential argument:
>> 	1) FAST processors require faster busses, or else getting away
>> 	from busses in the direction of mainframe-style architectures.
>
>Mainframes don't have busses?  
>
>What do they use instead?

The buss allows more than one device to communicate over the same path.  This
technology is used for improved economics.  Connectivity will easily dominate
the expense of a system where busses are not used.

The 'buss-less' connecting scheme provides seperate ports for each device.
Thus there is a dedicated communication path so that no device has to share
its path with other devices.  If there is no provision to hang more than
one device off of it, then it's not a buss, it's just a point-to-point
connection.

--Steve
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