Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!ucsd!usc!samsung!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: ERISC???
Message-ID: <1616@crdos1.crd.ge.COM>
Date: 14 Nov 89 21:18:50 GMT
References: <1989Oct19.155752.13028@mentor.com> <126596@sun.Eng.Sun.COM> <48135@bbn.COM>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Distribution: usa
Organization: GE Corp R&D Center
Lines: 14

In article <48135@bbn.COM>, slackey@bbn.com (Stan Lackey) writes:

|  The Alliant does fp in one cycle. In fact anything that uses BIT FP chips
|  that cycles even up to speeds of 20MHz or more can do it, provided the
|  operand passing is pipelined properly.

  Not having use an Alliant in several years, do they really do FP in
one cycle? Or produce one FP answer per cycle. Your pipeline comment
makes me think you mean the latter.
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon