Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!ucsd!usc!samsung!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: 55 MIPS & 66 MIPS
Message-ID: <1617@crdos1.crd.ge.COM>
Date: 14 Nov 89 21:28:38 GMT
References: <1358@bnr-rsc.UUCP>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: GE Corp R&D Center
Lines: 27

In article <1358@bnr-rsc.UUCP>, schow@bcarh61.bnr.ca (Stanley T.H. Chow) writes:

|  Other interesting question:
|  
|     Which system has a larger "domain" over which it actually
|     achives quoted figures?
|  
|     What other systems/chips/... are claiming over 50 MIPS?
|  
|     How do these systems compare in terms of cost (design and per unit)?

  Question one is the kicker. I don't care (as a user/buyer) how many
mips a CPU can perform, just how fast my stuff runs. For some programs
which don't overlap f.p. with other CPU, the Intel will not deliver full
potential. For other which do, particularly if the non-f.p. ops are the
kind which seem to require more than one RISC op to perform but might be
a single op in CISC, I would expect the Intel to look very good.

  Actually this gets beyond RISC/CISC discussion back to the "fast
serial vs. parallel" track, since the Intel gets the rating by putting
execution units in parallel. This implies that there are big losses of
performance if the compiler doesn't keep the mix right, etc.
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon