Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!boulder!stan!momma!stevec
From: stevec@momma.Solbourne.COM (Steve Cox)
Newsgroups: comp.arch
Subject: Re: RISC multiprocessors
Message-ID: <1989Nov15.040039.28570@Solbourne.COM>
Date: 15 Nov 89 04:00:39 GMT
References: <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM> <23963@cup.portal.com>
Sender: news@Solbourne.COM
Reply-To: stevec@solbourne.com (Steve Cox)
Organization: Solbourne Computer, Inc.
Lines: 19

In article <23963@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes:
>Snooping directly on the primary R3000 cache is indeed possible, but as I
>understand it, the degradation on CPU performance due to contention for the
>cache is signficant.  Plus, the R3000 cache is write-through, and a reasonable
>multiprocessor system needs write-back caches.  All multiprocessor R3000 system
>I'm aware of use second-level write-back caches.

second-level write-back caches?  so (correct me if i am wrong), there 
is a first level cache that is not connected to the shared memory bus.
how do these systems support cache coherency for data that is 
cached in the first level cache?  sounds pretty hairy to me. 
or am i missing something?


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steve cox			stevec@solbourne.com
solbourne computer, inc.
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