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From: nelson@m.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: Microprocessors: waste & utilizatio
Message-ID: <3300082@m.cs.uiuc.edu>
Date: 15 Nov 89 17:34:52 GMT
References: <31286@obiwan.mips.COM>
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Nf-ID: #R:obiwan.mips.COM:31286:m.cs.uiuc.edu:3300082:000:307
Nf-From: m.cs.uiuc.edu!nelson    Nov 14 07:46:00 1989


Although I have no experience with the VLSI "real world," I would say
  that we are looking at a transistor area (for CMOS) on the order of
  5%.  I would expect the figure for just the logic to be about 2.5%, but
  highly regular, packed structures such as on-chip cache certainly
  boosts that number up.