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From: dfields@urbana.mcd.mot.com (David Fields)
Newsgroups: comp.arch
Subject: Re: RISC multiprocessors
Message-ID: <1084@urbana.mcd.mot.com>
Date: 15 Nov 89 14:02:05 GMT
References: <sZLhtay00UkaIj6al2@andrew.cmu.edu> <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM>,
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Organization: Motorola MCD
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In article <sZLhtay00UkaIj6al2@andrew.cmu.edu>, bader+@andrew.cmu.edu
(Miles Bader) writes:
> mslater@cup.portal.com (Michael Z Slater) writes:
> > Plus, the R3000 cache is write-through, and a reasonable
> > multiprocessor system needs write-back caches.
> 
> Why?

If you don't have a write-back cache then you will stall every time
you fill up your write-post buffer.  Think about the number of cycles
to real memory, the burstiness of write traffic (a function call with
several args and register variables, although one would hope the args
are in registers, some of them will probably need to be written) and
the depth of the write-post buffer (2-4 words are reasonable).

Then play around with the numbers and you will understand.

Dave Fields // Motorola MCD //  !uiucuxc!udc!dfields