Path: utzoo!utgpu!watmath!att!occrsh!uokmax!apple!usc!cs.utexas.edu!asuvax!mcdphx!udc!chant!aglew From: aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) Newsgroups: comp.arch Subject: Re: RISC multiprocessors Message-ID: Date: 15 Nov 89 15:00:03 GMT References: <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM>, <1084@urbana.mcd.mot.com> Sender: aglew@urbana.mcd.mot.com Organization: Work: Motorola MCD, Urbana Design Center; School: University of Illinois at Urbana-Champaign Lines: 18 In-reply-to: dfields@urbana.mcd.mot.com's message of 15 Nov 89 14:02:05 GMT >If you don't have a write-back cache then you will stall every time >you fill up your write-post buffer. So make the write post buffers big enough that you don't stall very much. (I rather like the idea of a trickle-back cache, where write-back data is left in the cache for subsequent access, with only a tag put in the write-back queue. Plus combining in the write-back queue (two writes to same location do not both need to go through (modulo your consistency model)) this gets close to write-back, possibly with less control. But then, write-back isn't *that* hard to do. Norm Jouppi says it's easier than write buffering... -- Andy "Krazy" Glew, UIUC ECE aglew@uiuc.edu (afgg6490@uxa.cso.uiuc.edu) (Formerly of Motorola MCD Urbana)