Path: utzoo!attcan!sobmips!uunet!cs.utexas.edu!swrinde!ucsd!rutgers!cmcl2!edith!edith.ultra.nyu.edu!freudent From: freudent@eric.nyu.edu (Eric Freudenthal) Newsgroups: comp.arch Subject: Re: RISC multiprocessors Message-ID: Date: 16 Nov 89 13:14:57 GMT References: <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM>, <1084@urbana.mcd.mot.com> Sender: news@edith.ultra.nyu.edu Organization: New York University, Ultracomputer project Lines: 23 In-reply-to: aglew@urbana.mcd.mot.com's message of 15 Nov 89 15:00:03 GMT There is another well known solution to the problem of dual-porting a cache between a shared bus and a pe (processor). The idea is to use some sort of filter to keep bus transactions which do not affect the cache from reaching the cache. This solution is cheaper than building two identical caches and is equally effective. Build a conventional cache augmented with an extra copy of tag-store, which will be used as a filter. This is updated every time the real one is. Clearly, in the absence of cache-misses, the extra tag store is never updated. Bus transactions are looked up in this extra tag-store without disturbing the real cache if the address does not not match. If they do, then the real cache entry is updated or invalidated (similarly changing the tar-store copy). -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Eric Freudenthal NYU Ultracompter Lab 715 Broadway, 10th floor New York, NY 10012 Phone:(212) 998-3345 work (718) 789-4486 home Email:freudent@ultra.nyu.edu