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From: halliday@cheddar.cc.ubc.ca (Laura Halliday)
Newsgroups: comp.binaries.ibm.pc.d
Subject: Re: RISC vs CISC
Message-ID: <5672@ubc-cs.UUCP>
Date: 17 Nov 89 17:58:16 GMT
Article-I.D.: ubc-cs.5672
References: <29806@iuvax.cs.indiana.edu> <17075@netnews.upenn.edu> <1104@bridge2.ESD.3Com.COM>
Sender: news@cs.ubc.ca
Reply-To: halliday@cc.ubc.ca (Laura Halliday)
Distribution: comp.binaries.ibm.pc.d
Organization: UBC Computing Centre, Vancouver, B.C., Canada
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In article <1104@bridge2.ESD.3Com.COM> mbt@bridge2.ESD.3Com.COM (Brad Turner) writes:
>Based on my limited knowledge in the subject area I thought that the
>distinguishing characteristics of a RISC chip were the following:
>    o  Hardcoded logic.
>    o  All instruction execute in 1 clock cycle

RISC originally stood for Reduced Instruction Set Computer, with the idea being
that you could make a very simple chip with a small, simple intruction set,
run it *very* fast, and execute zillions of simple little instructions, for a
net increase in performance.

>It is the combination of the two above items that generally require
>the instruction set to be small. 

This has been changing. As chip people have figured out how to make more and
more complicated chips, the emphasis has indeed shifted from simple instruction
sets to as few clock cycles per instruction as possible. Personally, I think
it's time for a bit of a breather, so that we can figure out how to program such
computers effectively and make real use of their awesome power.

Too many systems team up 1990's hardware with 1960's software.

Perhaps this should be followed up in comp.arch.

...laura