Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!pilchuck!dataio!aez
From: aez@Data-IO.COM (Adam Zilinskas)
Newsgroups: comp.dsp
Subject: Re: 1 bit D to A ?
Message-ID: <2211@dataio.Data-IO.COM>
Date: 15 Nov 89 20:23:10 GMT
References: <8911091355.AA20559@en.ecn.purdue.edu>
Reply-To: aez@dataio.Data-IO.COM ()
Organization: Data I/O Corporation; Redmond, WA
Lines: 49

I think what the real mechanism used in 1 or low bit DAC is that 
they digital data is oversampled, passed through a smaller simpler
DAC and then low-pass filtered back to the desired shape. I have
hiding somewhere a couple of references to some ICCAD papers on
analog design where a company was using a 3-bit DAC, a cheapish
low-pass filter and some DSP techniques on the oversampled signal to
compensate for the low-pass.

Here is a very simplistic 1 bit DAC example:

digital bit -----|diode>-------+----+-------> "analog out"
                               |    |
                               -    -
                               C    R
                               a    e
                               p    s
                               -    -
                               |    |
                               -    -
                               =    =  < -- "ground"

To those that can't read my ASCII schematic, this is essentially a 
peak detector.

The Low pass filter is an RC circuit. To generate "max" analog output,
the digitial bit must always be one, "min" is when the digital bit is always
zero. Now anything in between will have a the digital bit being one for
a certain percentage of time (for 3/16*"max" output, a stream of 3 ones and
13 zeros should arrive at the each RC timeframe). The mechanism is very much
like a switching power-supply (a controlled amount of charge is pumped
out to maintain a desired voltage) except that the timeframe has to be
particularly high to be useful. 

Note that if you breadboard this circuit up, the analog output would not
be perfectly clean (due to the poor low-pass filter ;-). The technique
makes the DAC cheap (almost non-existant) but puts the burden upon the
low-pass filter (analog) or on the DSP technique (digital) to recover the
information.

Like a professor, I leave the mathematics as an exercize for the reader :-)
problem 1. Find a reasonable RC constant for 100 Khz DAC.
Problem 2. Determine the bit-period and frame size to generate a 50KHz 
	sine wave with 16 bits accuracy.
Extra Credit: Generate a Z-transform, DSP program... that will precompensate
	the 16 bit input to make this DAC work better.

			Adam Zilinskas
	"Gee this isn't a PLD, you shouldn't assume that Data I/O has 
	anything to do with it or has responsibility for it. :-) "