Path: utzoo!bnr-vpa!bnr-fos!bigsur!bnr-rsc!mark
From: mark@bnr-rsc.UUCP (Mark MacLean)
Newsgroups: comp.sys.m88k
Subject: Re: SERIALIZATION bit
Keywords: serialization, debuggers
Message-ID: <1361@bnr-rsc.UUCP>
Date: 13 Nov 89 18:33:56 GMT
References: <223@m1.UUCP> <1989Nov12.173826.19296@paris.ics.uci.edu>
Reply-To: mark@bnr-rsc.UUCP (Mark MacLean)
Organization: Bell-Northern Research, Ottawa, Canada
Lines: 13

In article <1989Nov12.173826.19296@paris.ics.uci.edu> Ron Guilmette <rfg@ics.uci.edu> writes:
>there is a control bit (in one of the control registers) that is said to
>be the "SERIALIZATION" bit.  The manual (cryptically) sez that setting
>this bit "serializes" the processor. 
>
>What I *really* want to know (besides *all* of the details) is whether
>or not this bit could be useful to debuggers (i.e. does it disable the
>otherwise confusing effects of pipelining).


What pipeline effects are confusing for debuggers?  When you do a trap instruction
(for a breakpoint) the processor gets serialized anyway, not leaving much around in 
the control registers to confuse users.