Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!tut.cis.ohio-state.edu!ucsd!helios.ee.lbl.gov!nosc!crash!orbit!pnet51!pj
From: pj@pnet51.orb.mn.org (Paul Jacoby)
Newsgroups: comp.sys.mac.hardware
Subject: Re: '030 burst mode (was Re: Mac IIci wait states)
Message-ID: <1465@orbit.UUCP>
Date: 12 Nov 89 03:05:31 GMT
Sender: root@orbit.UUCP
Organization: People-Net [pnet51], Minneapolis, MN.
Lines: 13

Noah@apple.com writes:
>>Yes, both the data and instruction caches are enabled and burst enabled
during the boot process.
<<
  So I assume that Jim Hamilton's "CacheControl" cdev just goes out to the
chip and resets the appropriate bit(s) to disable or re-enable the cache(s)?
  Another question: Are there any stats on how often the '030 Macs are able to
utilize burst mode?
.-----------------------------------------------------------------------------.
| UUCP: {rosevax, crash, orator}!orbit!pnet51!pj |  Working with idiots keeps |
| ARPA: crash!orbit!pnet51!pj@nosc.mil           |  my life interesting...    |
| INET: pj@pnet51.cts.com                        |                            |
`-----------------------------------------------------------------------------'