Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!tut.cis.ohio-state.edu!ucbvax!ucsfcgl!cca.ucsf.edu!rampil
From: rampil@cca.ucsf.edu (Ira Rampil)
Newsgroups: comp.sys.mac.programmer
Subject: 8530 SCC access
Keywords: SCC, serial
Message-ID: <2571@ucsfcca.ucsf.edu>
Date: 14 Nov 89 16:32:26 GMT
Organization: Computer Center, UCSF
Lines: 10


Does anyone know the mapping between the four registers per
channel mentioned in IM (ie Read(data,ctl), Write(date,ctl)) and the
eight READ registers and 16 WRITE registers that the SCC actually
has?  I need to RESET CTS IE and DCD IE in WR15 and then poll
RR0 (probably the IM ReadCTL) in a Time Manager Task to check the
current state of these input lines.  Please E-Mail or Post, as you 
desire!
Many Thanks,
Ira