Path: utzoo!utgpu!watmath!watcgl!watnext!lindsay
From: lindsay@watnext.Waterloo.EDU (Lindsay Patten)
Newsgroups: comp.sys.transputer
Subject: Re: Buffering Transputer Links
Message-ID: <12277@watcgl.waterloo.edu>
Date: 13 Nov 89 19:20:44 GMT
References: <1049@castle.ed.ac.uk>
Sender: daemon@watcgl.waterloo.edu
Reply-To: lindsay@watnext.Waterloo.EDU (Lindsay Patten)
Distribution: world
Organization: University of Waterloo
Lines: 19

In article <1049@castle.ed.ac.uk>, dil@lfcs.ed.ac.uk (David Laurenson) writes:
: I am trying to build a transputer link analyser that passively
: monitors the communications link between two transputers, and produces
: a high level (hopefully) form of debugging/performance monitoring.  I
: am currently trying to find a suitable differential driver/receiver
: pair that I can use that will not introduce more than 3nS skew.
: 
: I am currently looking at the uA9637AC and uA9638C pair, but I am
: unsure of their skew tolerance.   Has anyone already buffered the
: links successfully, and if so what chips did you use?

I'm probably being niave but, would C011 chips make this sort of thing
fairly easy?  I have to admit that I don't know what perfomance loss
they cause.

Lindsay Patten            "People are package deals - No substitutions allowed"
Pattern Analysis & Machine Intelligence Group                   lindsay@watnext
Department of Systems Design Engineering           lindsay@watnext.waterloo.edu
University of Waterloo              {utai|decvax|uunet}!watmath!watnext!lindsay