Path: utzoo!yunexus!ists!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!rice!titan!preston
From: preston@titan.rice.edu (Preston Briggs)
Newsgroups: comp.arch
Subject: Re: 55 MIPS & 66 MIPS [really: i960, i860, etc]
Message-ID: <3044@brazos.Rice.edu>
Date: 18 Nov 89 17:51:27 GMT
Article-I.D.: brazos.3044
References: <1358@bnr-rsc.UUCP> <31329@winchester.mips.COM> <22303@gryphon.COM> <3024@brazos.Rice.edu> <31659@winchester.mips.COM>
Sender: root@rice.edu
Reply-To: preston@titan.rice.edu (Preston Briggs)
Organization: Rice University, Houston
Lines: 18

In article <31659@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>In article <3024@brazos.Rice.edu> preston@titan.rice.edu (Preston Briggs) writes:
>>We've played some with an i860 on an evaluation board.
>>The supplied compilers didn't attempt to issue more than 
>>1 instruction/cycle (out of a max of three).  
>
>Note: I think this statement is offering data (thanx!) on a related issue,
>and did not confuse the two chips, but just to make sure,
>i860s and i960s are completely different chips.

Right.  I was just trying to cast aspersions on data that suggest we're
going to see an average of 2 instructions/cycle sometime this decade
(wow, big claim).  It might be a couple of years.  
The problem is lack of compilers, not the chips.

On the other hand, Multiflow has probably been doing it for years.

Preston