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From: phillips@convex.com (Steve Phillips)
Newsgroups: comp.arch
Subject: ETA10 (was Re: Surges)
Message-ID: <3217@convex.UUCP>
Date: 18 Nov 89 21:36:47 GMT
Sender: news@convex.UUCP
Reply-To: phillips@convex.com (Steve Phillips)
Followup-To: comp.sys.super
Organization: Convex Computer Corporation, Richardson, Tx.
Lines: 73


In article <150@csinc.UUCP>, rpeglar@csinc.UUCP (Rob Peglar x615) writes:

> In article <7000@pt.cs.cmu.edu>, lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:

[deleted comments about Cray]

> > CMOS isn't like that. It's asymmetric, and cares about transitions:
> > 0=>1 takes more power than 1=>1. So, one can write worst-case
> > programs, which generate on-chip noise (mass transitions on the wide
> > datapath), or which generate board noise and heat (mass transitions
> > on the address and data pins). I'm not sure what cache activity
> > generally produces the most heat: it may depend on implementation.
> > 
> (more deletions)
>
> > CMOS is wonderful, but the ECL/GaAs/BiCMOS folks talk an awful good
> > fight about how it's a different world on the other side of 50 MHz.
>
> Sure is.  The ETA-10 had this problem in spades.  This is why the
> ETA-10 air-cooled was limited to about a 12-13 ns clock (~80 MHz)
> before fratzing.  There was a 15ns model (the model R) under development
> when CDC killed it.
>
> The liquid-nitrogen cooled behemoths could have gone just about as
> fast as one dared.  The successor machine to the ETA-10G (the I
> model) was to be around 5 ns (200 MHz) in a breadbox-sized container
> of liquid nitrogen.  Folks were talking about a 500 MHz board, but
> that was just hall talk.
>
> Note, the parts were ASIC CMOS.
>
> [ deleted Neil quote ]
>
>-- 
>Rob Peglar	Control Systems, Inc.	2675 Patton Rd., St. Paul MN 55113
>...uunet!csinc!rpeglar		612-631-7800

The ETA10-E and ETA10-G machines were not LN2 cooled to prevent the
gate arrays from melting. While it is true that the LN2 removed the
heat generated, that was not the reason that LN2 cooling was chosen.
They were LN2 cooled because the gate delays were reduced by a factor
of 0.6 at those temperatures. This is due to the simple fact that
transistors switch faster at -190 degrees celsius than they do at room
temperatures.  

In addition, the minimum clock cycle was not limited by the increasing
amounts of heat generated as the clock cycle is reduced. It was
limited by the fact that the machine was designed to run at 7 ns in
LN2 and, if the clock was pushed beyond this, then long paths became a
problem. If we apply our 0.6 speed up factor in reverse ( 7ns / 0.6 ),
we get a minimum "warm" clock cycle of ~11.7 ns. 

It should be noted that the 7 ns clock cycle was chosen based on the
estimates of the speed of the process from our vendor. These estimates
proved to be wildly optimistic. Near the end of the design phase, a
new "improved" spec arrived and we suddenly found that our 7 ns
machine would run no faster than 14 ns. Over a two year period the
silicon process was improved and we eventually began getting arrays
that performed up to the original spec. This was one of several
reasons for the delayed introduction of the 7 ns ETA10.

Actually, getting rid of the heat in the air cooled machines was the
least of our problems. Lousy CMOS gate array output drive, poorly
terminated transmission lines, impedance mismatches, process
variations, and clock tuning were all more of a headache. These are
the type of problems that the 'ECL/GaAs/BiCMOS folks' are talking
about.


 Steve Phillips               | "The New Force in Supercomputers"    
 Convex Computer Corporation  | "We Will Win the Supercomputer Race" 
 phillips@convex.com          |        -former slogans of ETA