Path: utzoo!attcan!uunet!cs.utexas.edu!usc!henry.jpl.nasa.gov!elroy.jpl.nasa.gov!david
From: david@elroy.jpl.nasa.gov (David Robinson)
Newsgroups: comp.arch
Subject: R6000 vs BIT SPARC
Message-ID: <1989Nov21.015953.13817@elroy.jpl.nasa.gov>
Date: 21 Nov 89 01:59:53 GMT
Organization: Image Analysis Systems Grp, JPL
Lines: 16

Can anyone with any detailed knowledge compare the new MIPS R6000 with
the BIT 80Mhz SPARC (B5000)?  BIT is claiming 65 MIPS while the R6000
is rated at 55 MIPS.  I thought both the R6000 and B5000 were manufactured
by BIT and probably with the same ECL process.

I know most of the standard MIPS vs SPARC arguments (reg windows etc)
so I am interested in how the implementations differ and the types
of trade offs that were made.  An article in SunTech Journal (aka
Sun's trade rag) talks about the trade offs in their cache design.

Any comments?
-- 
	David Robinson		elroy!david@csvax.caltech.edu     ARPA
				david@elroy.jpl.nasa.gov	  ARPA
				{cit-vax,ames}!elroy!david	  UUCP
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