Path: utzoo!attcan!uunet!samsung!rex!ames!sun-barr!newstop!sun!amdcad!electron!tim From: tim@electron.amd.com (Tim Olson) Newsgroups: comp.arch Subject: Re: 55 MIPS & 66 MIPS Message-ID: <28107@amdcad.AMD.COM> Date: 19 Nov 89 22:06:52 GMT References: <1358@bnr-rsc.UUCP> <31329@winchester.mips.COM> <22303@gryphon.COM> Sender: news@amdcad.AMD.COM Reply-To: tim@amd.com (Tim Olson) Organization: Advanced Micro Devices, Inc., Austin, Texas Lines: 97 Summary: Expires: Sender: Followup-To: In article <22303@gryphon.COM> scarter@gryphon.COM (Scott Carter) writes: | The 960 CA can issue three instructions per | cycle to the chosen three of four execute units. I believe Intel has figures | showing that on the average they could infact issue two instructions per clock | _average_ [over what program set?], hence the 960CA can legitimately be called | 66 Native MIPS average with 99 Native MIPS peak. The i960CA decoder can dispatch up to 3 instructions per cycle. However, the decoder looks at 4 instructions at a time, and it appears that the decoder cannot be loaded with the next set of 4 instructions until the current set of instructions have all been dispatched. Therefore, the "99 Native MIPS peak" can only be attained for one clock cycle; the left-over instruction in the decoder would be dispatched by itself in the next clock cycle. In reality, it is "66 Native MIPS peak". | How this will work out in | "reality" who knows? I'm looking forward to Specmarks for a 960CA Real | System! Since the 960CA is targeted for embedded control applications, and has no MMU nor floating-point, I don't think you will ever see Specmarks for it. However, Intel released performance numbers for it at the i960CA announcement. The numbers were for a 33 MHz i960CA running with 64KB of 15ns SRAM and 1MB of 4-cycle inital access, 3-cycle subsequent access DRAM. The SRAM was used for instruction memory and the DRAM was used for data memory. The benchmarks run were Dhrystone 1.1, Buffer Copy, "Travelling Salesman" solution by simulated annealing, Pi (compute pi to 500 places), quicksort, bubblesort, integer matrix multiply, CCITT image compression, and Bezier curve calculation. Intel compared its i960CA board running this benchmark suite with a 68030 (20MHz), an i960KA(20MHz), and an Am29000(16MHz) board. However, the board they used to benchmark the Am29000 was not designed for performance; rather, it was designed to test the functionality of ADAPT (Advanced Development and Prototyping Tool) hardware debuggers. To provide a more fair comparison, I requested the benchmark sources from Intel, to run on a 30MHz Am29000 board (manufactured by YARC Systems). This board uses 2-way interleaved, 100ns DRAM memory for instructions and 35ns SRAM for data. I received sources for the non-proprietary benchmarks, compiled them with the current version of the MetaWare HighC29k compiler, and ran them on the YARC card. Here are the final results: Absolute Performance benchmark 68030 960KA Am29000 960CA 20MHz 20MHz 30MHz 33MHz quicksort (ms) 286 135 51 50 bubblesort (ms) 291 180 65 85 pi-500 (ms) 6999 3510 1398 1624 anneal (ms) 37210 20910 8119 8388 matmult (us) 186552 74873 49135 26898 dhrystone 1.1 5484 14196 44876 41600 Performance Relative to 68030 Board benchmark 68030 960KA Am29000 960CA 20MHz 20MHz 30MHz 33MHz quicksort 1.00 2.12 5.61 5.72 bubblesort 1.00 1.62 4.48 3.42 pi-500 1.00 1.99 5.01 4.31 anneal 1.00 1.78 4.58 4.44 matmult 1.00 2.49 3.80 6.94 dhrystone 1.1 1.00 2.59 8.18 7.59 ------------------------------------------------------- geom mean 1.00 2.07 5.11 5.20 Performance Normalized to 20MHz, Relative to 68030 Board benchmark 68030 960KA Am29000 960CA quicksort 1.00 2.12 3.74 3.47 bubblesort 1.00 1.62 2.98 2.07 pi-500 1.00 1.99 3.34 2.61 anneal 1.00 1.78 3.06 2.69 matmult 1.00 2.49 2.53 4.20 dhrystone 1.1 1.00 2.59 5.46 4.60 ------------------------------------------------------- geom mean 1.00 2.07 3.41 3.15 Thus, it would appear that the "66 Native MIPS", 33MHz i960CA is about the same performance as the 20 Native MIPS (18 VAX-equivalent MIPS), 30MHz Am29000. -- Tim Olson Advanced Micro Devices (tim@amd.com)