Path: utzoo!attcan!uunet!samsung!usc!apple!fox!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: R6000 vs BIT SPARC
Message-ID: <24316@cup.portal.com>
Date: 21 Nov 89 18:12:58 GMT
References: <1989Nov21.015953.13817@elroy.jpl.nasa.gov>
Organization: The Portal System (TM)
Lines: 26

>Can anyone with any detailed knowledge compare the new MIPS R6000 with
>the BIT 80Mhz SPARC (B5000)?  BIT is claiming 65 MIPS while the R6000
>is rated at 55 MIPS.  I thought both the R6000 and B5000 were manufactured
>by BIT and probably with the same ECL process.

I wouldn't put much signficance on those performance numbers.  The MIPS
rating is MIPS Co.'s rating of their *system* performance, and thus includes
the particular cache structure, memory system, etc.  The SPARC numbers
are just estimates based on looking at the CPU chip, and (I believe) neglect
any cache effects.  No one has yet shown a system based on the BIT SPARC
chips; MIPS has shown their system, but concedes that its not ready for
benchmarking.

Note that I'm not saying that the SPARC chip might not be faster; just
that with the information available, you can't tell.

The implementation differences are major.  The MIPS design includes some
cache control and MMU logic on the CPU chip, while the SPARC design provides
absolutely no support for MMU or cache.  The MIPS design includes a bunch
of ECL gate arrays to hook up the cache RAMs to the processor.  Perhaps
because they included more functions on the CPU chip, the MIPS design is
initially rated at 66.7 MHz, while the SPARC design is rated at 80 MHz.

Michael Slater, Microprocessor Report    mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto, CA 94306
415/494-2677    fax: 415/494-3718