Path: utzoo!attcan!uunet!aplcen!samsung!cs.utexas.edu!rice!uw-beaver!ubc-cs!alberta!calgary!cpsc!deraadt
From: deraadt@cpsc.ucalgary.ca (Theo Deraadt)
Newsgroups: comp.arch
Subject: Re: RISC multiprocessors
Message-ID: <2118@cs-spool.calgary.UUCP>
Date: 20 Nov 89 14:33:54 GMT
References: <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM> <23963@cup.portal.com>
Sender: news@calgary.UUCP
Lines: 9

In article <23963@cup.portal.com>, mslater@cup.portal.com (Michael Z Slater) writes:
> Plus, the R3000 cache is write-through, and a reasonable
> multiprocessor system needs write-back caches. 
> Michael Slater, Microprocessor Report   mslater@cup.portal.com

As long as they are physical write back caches and not virtual. Unless you
like flushing huge virtual writeback caches everytime you context switch
and mapin your next process.
 <tdr.