Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!gem.mps.ohio-state.edu!apple!vsi1!ubvax!ardent!mac From: mac@ardent.com Newsgroups: comp.arch Subject: BIT parts (was Re: ERISC???) Message-ID: Date: 20 Nov 89 23:45:33 GMT References: <1989Oct19.155752.13028@mentor.com> <126596@sun.Eng.Sun.COM> <48135@bbn.COM> <1616@crdos1.crd.ge.COM> Sender: news@ardent.UUCP Reply-To: mac@ardent.com (Michael McNamara) Distribution: usa Organization: Ardent Computer Corporation, Sunnyvale, CA Lines: 28 In-reply-to: davidsen@crdos1.crd.ge.COM's message of 14 Nov 89 21:18:50 GMT In article <1616@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) writes: > In article <48135@bbn.COM>, slackey@bbn.com (Stan Lackey) writes: > > | The Alliant does fp in one cycle. In fact anything that uses BIT FP chips > | that cycles even up to speeds of 20MHz or more can do it, provided the > | operand passing is pipelined properly. > > Not having used an Alliant in several years, do they really do FP in > one cycle? Or produce one FP answer per cycle. Your pipeline comment > makes me think you mean the latter. If Alliant is using the same BIT parts we use (B2110A/B2120A), yes the parts themselves complete every floating point operation in a maximum of 50ns, excepting divide & square root. To deliever that performance, Alliant & we & everyone else must insure that operands get to the chips, and results get back to memory/cache/register file; this data piping is the necessity for pipelining. -mac -- Michael McNamara (St)ardent, Inc. mac@ardent.com